Brendan Lynskey

Staff Engineer · Blaize (formerly Thinci)

LeedsHardwareSoftware and AI

Blaize makes energy-efficient SoCs for machine learning and computer vision. Dual role: software/AI engineering and hardware systems engineering.

• Building an agentic analytics system in Python with LangGraph, MCP, vLLM and Qwen models on DGX Spark, including automated evaluation regression-test suites; video analytics; accelerated development using Claude.
• Responsible for the System-on-Module that won the 2022 Edge AI and Vision Product of the Year award and a 2022 Sacramento Business Journal Innovation Award, plus its commercial and industrial variants.
• Power delivery (multiphase DC-DC, PoE, flyback), SI/PI and thermal for PCIe accelerator cards and modules with PCIe Gen3, USB 3.0, MIPI and LPDDR4, from concept through layout (HDI), bring-up, environmental test, conformal coating and EMC pre-compliance.
• Simulated and measured power networks, high-speed serial links and DDR interfaces in the time and frequency domains (Cadence Sigrity tools, 3D extraction). Reviewed SoC FC-BGA substrates.
• Analysed SoC SystemVerilog as part of system debug; built a Zynq UltraScale+ MPSoC prototype (PetaLinux); analysed competitor systems; ML development and benchmarking in Python.
• Tooling: a Python utility that derives PI requirements from raw power-simulation data using STFT analysis; PowerShell/SKILL release tools for Cadence; VS Code extensions in TypeScript.
• EDA: Cadence suite (DE, Allegro, PowerSI, SystemSI, PowerDC, OptimizePI), LTspice/LTpowerCAD II, SIMetrix/SIMPLIS.

Senior Design Engineer · Imagination Technologies / MIPS

LeedsFPGA and SoCHardwareDSP

Debug and probes team.

• High-performance CPU debug systems on Xilinx 7 Series: AXI, PCIe bus mastering, DDR3, Aurora, XADC analogue capture, embedded Linux (U-Boot, Buildroot).
• FPGA prototyping platforms for IP cores on UltraScale and AWS EC2 F1 (UltraScale+), covering the whole stack from RTL to Linux device driver.
• On-chip instrumentation cores, and software transactors that drove RTL simulation and emulation over TCP/IP (Verilog/C VPI PCIe transactors).

Senior Consultant · Red Embedded

SaltaireFPGA and SoCHardwareDSP

Consultancy across hardware, FPGA and software.

• FPGA broadcast product using Xilinx video IP (3G-SDI, scaler), AXI and embedded Linux (VHDL, C).
• Two FPGA DSP projects with Sagentia, for geophysics and medical applications (Verilog, VHDL, System Generator).
• High-performance PC-based DSP (video processing) for professional broadcast (Python, C++); automated RF testing for powerline comms (Python).

Principal Engineer · Pace

SaltaireFPGA and SoCDSP

Delivered complete FPGA systems for cable headend and transmodulator products.

• High-performance packet classifiers and switches, with DDR interfaces, an on-chip bus and large FIFO structures.
• DOCSIS QPSK/16-QAM burst receiver and J.83 64/256-QAM modulator PHY and MAC layers; Gigabit Ethernet; high-speed inter-FPGA links; embedded MicroBlaze/PowerPC systems; clock-domain crossings.
• Overhauled the group's verification strategy.
• Also a CableCARD (M-Card) interface and a BER instrument for satellite receivers.

Senior Engineer · Comodo

BradfordFPGA and SoCCryptography

Front-end design of a 0.18 µm cryptographic SoC (TPM / security token). Designed and integrated an in-house crypto processor (RSA, SHA-1, 3DES, AES, PRNG) with an 8051 CPU, USB, smartcard and LPC interfaces.

Engineer · Pace

SaltaireHardwareFPGA and SoC

Built Pace's first hard-disk MPEG-2 prototype (PCB, FPGA) and FPGA blocks (DVB, UDMA-66) for a 3DES-protected PVR, which won the company's Most Inspiring Invention award in 2000. Also an ADSL–HPNA set-top-box bridge, and an IrDA handset for speech/speaker recognition.

Hardware Engineer · Thales

StockportHardwareFPGA and SoC

Designed the Sonar 2076 data transceiver (1 Gbit/s fibre optics, ECL serial datapath, Fibre Channel, SHARC processors); worked on a DSP co-processor ASIC.