Brendan LynskeyCV
Experience and education
Experienced engineer working in AI systems (LLMs, agents, MCP, Python) with a background in FPGA, DSP, hardware and power.
Portfolio
Brendan Lynskey
A staff-level engineer across hardware (RTL and FPGA, DSP, signal integrity) and agentic AI.
More than 25 years in hardware, and I write the software too. Here are sixteen interactive explainer sites in four tracks, built for my own learning and still being worked through, deck series from signal integrity to agents, and the simulators and RTL behind them. Every number comes from tested code or a cited, dated source, and every model is checked against something independent of it.
16 interactive sites4 tracks41 LLM sub-hubs, 275 decks17 signal-integrity decksEvery number tested or sourced
Digital Twin New version coming soon
Ask about my career
A chat agent, trained on my career, that answers questions about it. Built in Ed Donner's Proficient AI Engineer curriculum.
Home ground
Hardware, DSP and signal integrity
Where most of my career has been: channels and equalisers, RTL and its verification, accelerator simulators and the DSP behind audio. Each card links a series hub; the hubs link the decks.
Signal Integrity & High-Speed Digital Design
Getting a signal from one chip to another intact: transmission lines, return paths, materials, vias, crosstalk, jitter, power integrity, timing budgets, de-embedding and channel operating margin. Every number is computed by a model and checked against published worked examples.
17 decks, 188 slides; 20 cross-checks against published results, the largest difference 2.44 %.
SerDes, SoC and Matrix Methods
One 28 GBd backplane channel taken end to end, from S-parameters through CTLE, FFE and DFE to a closed link budget; the S-, Z- and Y-parameter and filter theory underneath it; and a Modern SoC Design series on packaging, chiplets, NoCs and memory.
The noise budget lands 1.36 dB short of 10⁻¹², and seven remedies are priced in dB.
Matrix Methods in Network ParametersMatrix Concepts in Digital FiltersModern SoC Design
RTL: interview challenges and free SystemVerilog simulators
Nineteen RTL interview challenges put through Icarus Verilog, Verilator, the Vivado simulator and slang, construct by construct, with every error message recorded; plus synthesisable RTL with its own verification suites.
All nineteen challenges pass (nine in Verilator, ten in xsim).
RTL / LLM accelerator challengesFPGA challengesTransformer decoder in RTLMatrix multiplier unitsRISC-V SoC
FHE Accelerator Simulators
Simulating a fully homomorphic encryption accelerator running CKKS bootstrapping: the workload, the anatomy of bootstrapping, a SimPy accelerator model with a live in-browser simulator, optical NTT engines and the design space.
Five decks; the simulator has a bit-exact JavaScript port and replays OpenFHE traces.
Simulation Engineering Toolkit
The engineering around a hardware-architecture simulator: Rust and PyO3, SystemC TLM-2.0, DRAM/HBM modelling, a cocotb/Verilator verification bridge, Jenkins, specifications and test plans, PyTorch and ONNX front ends, measurement tools and power, performance and area.
Fourteen decks, with five code repositories behind them.
DSP, neural sound synthesis and audio plugins
A twelve-part interactive series on how machine learning makes sound, an audio plugins hub with a JUCE tutorial and seven example plugins, and browser synthesisers, analysers and guides to the transforms. Every sound is synthesised live in the browser.
Twelve parts; the DSP & Music index lists 50 projects in 8 areas.
Compute in Transit
Can useful work be done on LLM training and inference traffic while it crosses a link? Five decks on a photonic link module (arXiv:2608.21536), its operations-per-byte budget, frequency-domain gradient compression and a fixed-band experiment, with a results site.
The answer at this scale is negative, and the series says so.
Hardware index: RTL, RISC-V, Arm and more
Everything else in hardware: a RISC-V SoC built from separately verified subsystems, Arm Cortex-M, Cortex-A, Neoverse, AMBA and system IP series, dividers, CORDIC and NN number formats in SystemVerilog, Galois fields, optical technology and power electronics.
The Hardware index lists 52 projects.
Interactive sites
Sixteen sites, four tracks
I built these sites for my own learning, and I am still working my way through them. Each one is a computed, animated reading experience: the animations are drawn from a tested model, not hand-made. Every site's header has a menu to all the others, and every repository ships its models, fixtures and CI.
Foundations
One small model, end to end
Foundations › Decoder
How it runs, one forward pass
How this is checkedThe TypeScript transformer in your browser is checked against PyTorch, operation by operation, to within 1e-5, and the animations' frames against a float64 PyTorch run of the same seeded weights.
Foundations › Training
How it learns, from one step to many GPUs
How this is checkedA NumPy reference of the trainer matches PyTorch autograd (to 1e-12) and torch.optim, and the trainer in your browser matches that reference step for step.
Hardware
The machines underneath, chip to rack
Hardware › Kernels
How a GPU executes the maths
How this is checkedThe GPU model is checked against the CUDA Programming Guide's worked examples (coalescing, bank conflicts, occupancy), and its TypeScript port reproduces the Python reference exactly.
Hardware › Systolic
Inside a matrix engine
How this is checkedThe cycle-accurate model's output-stationary frames match a SystemVerilog array simulated in Verilator 5.020 on every accumulator after every clock edge: 613 values, 0 mismatches.
Hardware › Accelerators
The families of AI chips
How this is checkedEvery specification carries its source and the date it was read, vendor claims are never used as inputs, and the model is checked against published capacity, throughput and latency figures.
Hardware › Racks
GPUs, networks, power, cooling at scale
How this is checkedEvery hardware figure carries its source and the date it was read, and the model is checked against published rack, switch and fabric totals that it does not take as inputs.
Inference
Serving models at scale
Inference › Serving
How real systems generate text
How this is checkedThe serving simulator in chapters 11–14 is Disaggregated_Inference_Sim's own engine, copied byte for byte from a pinned commit, and CI requires every request's timestamps to match its Python original; the tiny model's cached logits are bit-identical to full recomputation.
Inference › Architectures
How model designs differ
How this is checkedEvery value links to its source, and the modelled parameter count of 80 of the 86 open models whose published weights can be counted is within 0.5% of those weights at a pinned commit.
Inference › Numerics
Number formats and quantisation
How this is checkedEvery code of every format up to 16 bits is checked against numpy and ml_dtypes, and the TypeScript port in your browser reproduces the Python reference exactly.
Inference › Trade-offs
Which lever helps which metric
How this is checkedFor every one of the 350 sweep points, the simulator's JavaScript engine (the one the what-if runs in your browser) reproduces the recorded TTFT, TPOT and ITL percentiles of the Python run exactly.
Agents
Building on models
Agents › Harnesses
The loop between a model and the world
How this is checkedAgent_Loop_Sim's Python reference and the TypeScript port in your browser produce the same events, token for token and float for float, and three recorded runs of a small open-weights model are replayed token for token.
Agents › Protocols
MCP, transports, auth and A2A
How this is checkedThe engine sends the same 160 messages as the official MCP Python SDK (mcp 2.3.0) over 18 recorded sessions, and the same 56 as the official A2A SDK (a2a-sdk 1.2.2), compared as JSON.
Agents › Context
Retrieval, memory and context engineering
How this is checkedEvery retrieval number is measured on 200 SQuAD questions with real MiniLM embeddings and recorded reranker scores, and the TypeScript engine in your browser reproduces the Python reference exactly, with no tolerance.
Agents › Orchestration
Graphs, multi-agent patterns, durability
How this is checkedEach of 39 sessions also runs in real LangGraph 1.2.14, and after every one of 71 operations its whole checkpoint history equals the engine's.
Agents › Evals
Measuring agents
How this is checkedThe estimators are tested against scipy and statsmodels on a synthetic benchmark whose truth is known, and the TypeScript engine in your browser reproduces every Python fixture bit for bit.
Agents › Security
Threats and defences
How this is checkedThe trifecta check agrees with an exhaustive search on all 256 tool subsets, and the TypeScript engine in your browser reproduces the Python reference's fixtures exactly.
Showcases
Hardware agents and compute experiments
HW Design-Space Agent
A LangGraph agent that explores hardware design trade-offs from one spec down a fidelity ladder to synthesis, with every number from a recorded run.
Compute in Transit: results
Can a fixed frequency band replace DeMo's top-k? An experiment, emulated optics and a training-transit simulation, with an honest negative result.
Verification
How I check the numbers
A model that agrees only with itself proves little, so every site is checked against something independent of it. Four examples, quoted from the sites:
Against RTL613 / 0
Systolic: “compares every accumulator after every clock edge with the model: 613 values, 0 mismatches”, in Verilator.
The check →Against LangGraph39 sessions
Orchestration: real LangGraph 1.2.14. “After each of the 71 operations”, the whole checkpoint history is compared.
The check →Against the official SDKs160 messages
Protocols: “the engine must produce the same 160 messages, compared as JSON with request IDs renumbered”.
The check →Against PyTorch1e-5
Decoder: the TypeScript transformer is “checked against PyTorch fixtures, operation by operation, to within 1e-5”.
The check →Deck library
The index hubs
Lecture-style slide decks go deeper than the sites. These indexes list them; the counts are taken from each index's README when this page is built.
LLMs
The main index: the interactive sites, then sub-hubs from transformer internals and GPU hardware to retrieval, agents, evaluations and safety.
41 sub-hubs · 275 decksHardware
RTL, RISC-V and Arm, SoC design, arithmetic units, optical technology, signal integrity and power electronics.
52 projectsDSP & Music
Synthesisers, analysis and effects, audio plugins, signal-processing guides and neural audio synthesis.
50 projects · 8 areasSoftware
CI/CD, Jenkins and GitHub Actions, identity and authorisation, cloud, web, algorithms and tooling.
110 projectsMathematics
Cryptography, coding theory, quantitative finance, mathematics for machine learning and historical mathematicians.
39 projectsMethod
How this is built
I choose the topics, write the specifications and set the rules for verification: every number on these pages comes from tested code or a cited, dated source, every browser port must reproduce its Python reference, and every model is checked against something independent of it. I check the numbers, and I own them.
The building is done with Claude (Anthropic's Claude Code) as an agentic engineering workflow. One session plans the work and writes a brief; another carries the brief out; the first then checks the result against the brief before anything is published. Every commit made this way carries a Co-Authored-By: Claude line, so the split is visible in each repository's history.